A distinguishing feature is the extensive use of the Verilog Programming Language Interface (PLI) . This allows for a mixed hardware/software environment where users can develop "virtual testers" to evaluate complex test strategies.
The text treats testing and testability as integral parts of the digital design process rather than afterthoughts.
The book by Zainalabedin Navabi (2010) is a comprehensive guide that bridges the gap between digital design and testing methodologies. Unlike traditional texts, it uses Verilog HDL to describe and simulate test hardware, making complex concepts like fault simulation and test generation more practical and less ambiguous for designers. Core Features and Methodology Digital System Test and Testable Design: Using ...
Scan architectures, RT-level scan design, and Boundary Scan (JTAG).
Gate-level faults, fault collapsing, and structural modeling in Verilog. A distinguishing feature is the extensive use of
Are you interested in a specific from the book, like BIST or Boundary Scan , for a more detailed breakdown? Courses Syllabus – Monsoon 2024 - pgadmissions@iiit.ac.in
Verilog is used to describe the internal architectures of Built-In Self-Test (BIST) and Design for Testability (DFT) . This helps engineers evaluate hardware overhead and timing feasibility, which is critical for System-on-Chip (SoC) designs. The book by Zainalabedin Navabi (2010) is a
Memory fault models, MBIST (Memory BIST) methods, and functional procedures.